Surface mounting of electronic components is well developed in automated package assembly systems. Integrated circuits are made up of devices such as transistors and diodes and elements such as resistors and capacitors linked together by conductive connections to form one or more functional circuits. The devices are built on wafers, or sheets of silicon with a surface that is subject to a series of fabrication steps to form a pattern of identical integrated circuits separated from each other by a repeating rectangular pattern of scribe lines or saw streets in the surface of the wafer that serve as boundaries between the chip or die. At a late stage in a fabrication process the singulated die from the wafer is bonded to a substrate to form an IC package.
Conventional flip chip technology generally refers to any assembly where the active side of the integrated circuit die is attached to a package substrate or printed circuit board (collectively referred to as a PCB). In connection with the use of flip chips, the chip is provided with bumps or balls of solder (hereafter “bumps” or “solder bumps”) positioned in locations on the active side designed to correspond to the interconnect areas or pads on the surface of the circuit board. The chip is mounted by registering the bumps with the board such that the solder bumps become sandwiched between the pads on the board and the chip. Heat is applied to the assembly to a point at which the solder is caused to melt, flow, and contact fully the pads on the board (referred to as reflow). Upon cooling, the solder hardens, thereby mounting the flip chip to the board's surface. Conventional underfill materials are used in several distinct approaches and are applied to a mounted chip to provide protection of the chip against chemical attack, moisture, radiation, air-borne contaminants, and the like, as well as against mechanical shock, vibration, and temperature cycling encountered in transit as well as use. A conventional capillary flip chip underfill process entails the steps of alignment of chip and circuit board, flux dispensing, solder reflow, flux cleaning, underfill application, underfill flow and curing.
Underfill materials used in chip packages serve functions to protect the solder joints that interconnect the chip and package or board from environmental factors such as moisture and contaminants and to redistribute mechanical stresses, which in turn increases device lifetime. Protection is provided for the chip against contaminants such as moisture and resulting corrosion of the metal interconnects. However improper selection of adhesives can result in flip chip package failures in several modes, such as shrinkage, delamination, hydrolytic instability, corrosion, and contamination by the underfill.
Chip underfill materials are designed to avoid imparting stress between the adherends as a result of differential coefficients of thermal expansion between the chip, interconnects, underfill and substrate. Failure modes due to stresses become more prevalent if the substrate is organic and as device size increases. A chip underfill must provide the function of adhering to the substrate, which may or may not be coated with solder mask; metal alloy or organic interconnects; and the integrated circuit die (chip), typically comprised of silicon or other inorganic species and may or may not be coated with an organic passivation layer.
In one of two principle ways to package electronic components, the components are soldered to the same side of the board upon which they are mounted. These devices are said to be “surface-mounted”. Two types of conventional underfill materials are in practice for use with surface-mounted devices: capillary flow and “no flow” types. Detailed descriptions of these technologies can be found in the literature. For example, see John H. Lau's book Low Cost Flip Chip Technologies for DCA, WLCSP and PBGA Assemblies, McGraw-Hill, 2000. For both of these technologies, heat is typically used to either cure a liquid thermosetting formulation or laminate a solid film into the assembly. Vacuum is sometimes used to remove air voids from the system. The underfill is typically applied on the surface mount (SMT) assembly line for chip in-package or chip on-board. The use of the traditional flow and no-flow underfills requires several steps on the SMT line, and this process is usually the bottleneck on these microelectronics assembly lines.
Flip chip type electronic packages suffer from sensitivities to impact and thermal stresses. These components typically fail at the electrical interconnects (such as solder bumps), or the dielectric layers on the silicon. An underfill is typically employed to secure the solder joints and protect the silicon die from exposure to extreme stress and/or corrosive environments.
Uncured liquid underfills are typically dispensed after the electrical interconnections are made, and cured to provide a mechanical bond between the die and board. The underfills also mechanically brace the solder and die, transferring stress away from the areas most prone to failure.
Another type of underfill is the wafer applied solder brace coating, which like an underfill, braces the solder and reinforces the die. But unlike liquid dispensed underfills, the wafer applied solder braces do not form a bond between the die and board. Wafer applied solder braces also are applied prior to bonding of the die to the board, typically at the wafer level (prior to dicing).
There are several methods of coating a wafer level solder bracing material. One method is to coat the wafer uniformly with the bracing material, then pattern holes into the coating by laser drilling or UV exposure. The subsequent holes are then filled with solder to make the electrical interconnect. This method has difficulties with alignment; the opaque coating material covers the entire surface of the wafer, and alignment of the drilling or UV exposure tools is made difficult. Further issues are related to cleaning the residue in the patterned holes for efficient soldering.
Additionally, passivation films and other semiconductor die coatings are commonly used as a barrier to physical damage and environmental contaminants. In the manufacture of semiconductor devices, the entire top surface of the wafer is often coated with a passivation film following the formation of the final metal layer. The passivation film is an insulating protective layer that minimizes damage to the dies during assembly and packaging. Passivation film may comprise inorganic compounds such as phosphosilicate glass and silicon nitride or organic compounds such as polyimides. The polyimide film is spun on to the wafer as a liquid polyamic-acid precursor. During high temperature curing or with the aid of a photoinitiator, the polyamic acid undergoes a chemical change called imidization that causes it to become the solid polyimide film.
Further, dielectric layers are provided to isolate the various electrical components on the die and provide an electrically insulating function. Vias are created through the dielectric layer to enable electrical interconnects to be established through the various layers of the chip package through standard photo-resist processing.